Introductions Thread

Place to introduce yourself…


Hi! I’m DJ, creator of DJGPP and current owner of gEDA, hardware hacker, and glibc developer (including glibc riscv maintainer). I’ve got a small number of riscv systems, one is the leading package builder for the ongoing “Fedora rocks” koji system (


Hi everyone! I’m Matthew Miller, Fedora Project Leader. I saw a number of RISC-V talks at Open Source Summit and got all excited about it, and realized that there are a lot of people in the project also excited but not a lot of coordinated communication. So here we are now!

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Hello world. I’m Kevin Fenzi (or nirik on matrix/irc). My day job is wrangling Fedora infrastructure and release engineering, but I also like playing with cool new hardware and helping to bring it into the Fedora community. I’ve been helping the mobility sig out of late with pinephone efforts (can’t wait for the pinephone pro!) and looking forward to playing more with risc-v.


Hi, I’m Richard, I did the first port of Fedora to RISC-V back in 2016: GitHub - rwmjones/fedora-riscv-bootstrap: Bootstrapping Fedora on RISC-V First successful rpmbuild on RISC-V | Richard WM Jones

I now have 6 RISC-V machines at home, 2 x HiFive Unleashed, 2 x HiFive Unmatched, BeagleV Beta, and PolarFire. (That’s not including FPGAs running RISC-V cores, of which I have several more)


Hi, I am Dan Horák, the main person behind Fedora for POWER and mainframes (aka s390x). I have “baby-sit” the secondary “ppc” and “s390” koji instances for many years before they were merged into the primary Fedora koji instance. I spent my time fixing bugs, porting unsupported packages, writing helper scripts, doing composes, simply almost everything between a source rpm and installable product. I prefer dog-fooding, so I type this message from my Power9 based Talos workstation running Fedora 34 :slight_smile: But I am still waiting for my first RISC-V hardware.


Howdy. I’m Al Stone, aka “ahs3”. Some people collect bobble head dolls, some people collect stamps, I tend to collect interesting technologies. I got started with RISC-V via a colleague (I’ll let them introduce themselves) and ended up helping with the platform specifications that are being written; I helped with similar specs for the Arm architecture, so it just seemed a natural thing to do. I do have a BeagleV on my desk, and have arranged for some SiFive boards to show up. I’ve been looking at some of the edk2 and ACPI code for RISC-V and at some point hope to have enough time to contribute more to those efforts so that things like booting Fedora become dead simple.


Hey, I’m Jon a hardware hobbyist who works with networking stacks by day. Super into the idea of using open ISAs to thwart hardware supply-chain attacks. I wrote a terrible midterm paper on the topic while I was in school that I’m really proud of: somlo_review/review_somlo_fpga.pdf at main · jontrossbach/somlo_review · GitHub


Hi all - This looks like a fantastic group!

I have gone by Jefro since the late 1980s on usenet & IRC. I was a technical writer for about 20 years in software & dev tools as well as hardware, both fabless (Transmeta) and otherwise. I shifted careers in 2011 to spend 8 years at Intel launching and helping to run the Yocto Project, and also helped out with Zephyr, ACRN, Kata Containers, and several other projects as a community & program manager. I recently spent two years at the Linux Foundation as a PM on RISC-V International, helping to organize under LF, build the organization from 2 to 7 people, and transition to Switzerland. I’m at Red Hat now working on community engagements for automotive.

I see a very bright future for RISC-V and I’m looking forward to helping make Fedora the de facto distro for Linux-capable RISC-V systems. Hardware wise, I do have a few of the Sparkfun Redboards in a box, but my input these days is largely administrative rather than technical. Very glad to be part of this community.


Hi, I’m Gabriel Somlo, author of linux-on-litex-rocket (rv64gc RocketChip and stock Linux support for the LiteX SoC).

I added rv64gc support to LiteX with the express purpose of eventually booting Fedora on it, which is currently a “work in progress” :slight_smile:

My interest is in buildig a fully self-hosting software+gateware stack, which will one day hopefully also include physical hardware (i.e., silicon).


Hi, I am David Abdurachmanov (aka davidlt), I jumped into Fedora/RISCV initial bootstrap few days after Richard made a blog post about it. Not sure how I got to the blog post, but most likely it was Hacker News. I dived deep into it.

I have been leading Fedora/RISCV project working on porting, testing, running Koji infrastructure, building packages, fixing them, building repositories and disk images, etc. Thus feel free to blame me if something got broken or you didn’t get an update for your package :slight_smile: I think… we have been doing Fedora/RISCV for 5+ years now. I am one of those people who had been running “RISC-V PC” for years now and can even run 4K movies (well, thanks for GPU video decode acceleration).

Years ago (back at CERN) I used to work on software release management and experimental stuff (Intel, AMD, IBM, ARMv8 64-bit). I especially pushed ARMV8 64-bit/AArch64 in early days before we even had hardware available (I recall 2 weeks waiting for GCC to compile on the simulator). That’s what started all this craziness: AArch64 and “building boring systems”.

These days I work for SiFive (the ones who made Unleashed and Unmatched) and that involves OpenEmbedded (OE). I do have Unleashed, Unmatched, Icicle Kit and BeagleV on my desk. Don’t have any Allwinner D1, but that is a complicated SoC.

The goal is to make RISC-V (riscv64) the natural citizen in Fedora arch club. How/When/How much energy that will cost is still unknown.


Hi, I am Jwy, currently an intern at PLCT lab and an undergraduate at Tongji University.

I got a D1 board for my OS course assignments and then I got interested in RISC-V. Then I learnt about Fedora/RISCV after I joined PLCT, and I was asked to watch the development progress of the Fedora/RISCV project.