I have been thinking about disabling LTO (globally) for riscv64 for some weeks/months now. All Fedora/RISCV builds (currently) happen natively on SiFive HiFive Unmatched boards. The SoC (FU740) in Unmatched does not have a strong single thread performance. There are no other boards on the market (available now or in near future) that have significant improvement in the single threaded performance. LTO hits us hard as it’s mainly single threaded, and it typically requires more memory. Even running 64-core SOPHGO SG2042 with T-HEAD C920 cores we only would be getting 4-5x increase in build packages for a very large packages (e.g. GCC). We continue to be bottle-necked by a LTO link stage, which in some cases could take even hours. Most likely this is not a problem once we get newer hardware in 1-2 years. SOPHGO recently announced SG2380 (2.5GHz 16-core SiFive P670 OoO cores) to be available on the board next year. There is also Ventana with server SoC/chiplets, but unknown when that would be available or reachable for majority of folks. There is also SG2044 (updated SG2044) scheduled for next year and might improve things. Most of these things are most likely towards the end of next year (if it doesn’t slip into 2025).
We (RISCV) does not have ld.gold linker support. To my knowledge no company is actively working on it (ever). PLCT listed it in their roadmap for 2023, but reading their weekly minutes there are no activities on this item. I also looked at RISE ( https://riseproject.dev/ ) priorities for 2023 2H and 2024 1H, and their JIRA tickets. This is not on any list. Not having ld.gold means we aren’t supporting LTO with LLVM/Clang + binutils (ld.bfd) toolchain setup today (well, ever).
The linkers that are actively being worked on for RISCV are ld.bfd, lld, and mold.
Disabling LTO means we could produce more builds per day, which is highly beneficial for us (it’s hard for us to keep up with upstream Koji).
Are the any with a strong objections on this?
Thanks for the input.