Hi, folks! Last month I was at the RISC-V Summit Europe, Paris. I wrote this (long) report for Red Hat engineering. I also wanted to send it to the Fedora community, but the past weeks were quite hectic. I finally got to it. Here we go!
Introduction
The RISC-V Summit aims to bring RISC-V hardware vendors, IP vendors (those who design and license RISC-V processor cores and peripherals), academic researchers, and software vendors together. There’s a European and a North American (NA) version of this event. The European variant has an academic bent to it compared to its NA cousin, which is run as a traditional Linux Foundation event. For example, the European event asks you to write a two-page extended abstract—a mini technical paper that is formatted like a scientific journal article. Poster presentations are also big here, a common feature at academic conferences.
The event location was a large industrial science park in Paris. It has auditoriums, and other amenities suitable for a conference; it also has a decent planetarium. It was a four-day conference, and the first day was for RISC-V International (RVI) members only. RVI governs the RISC-V instruction set architecture (ISA). The first day’s agenda was driven by various technical working groups. The topics were processor designs, status of in-flight ISA extensions, chip verification, and more. These sessions are recorded, but active participation in the room was for RVI members only.
The main conference started on the second day, with traditional keynotes, talks, panels, and demos. There were some inevitable marketing-style talks, but there were also many technical deep-dive sessions. A novel element for me was the above mentioned poster sessions, where people summarize their topic in a one-pager, and print it out in a large, A0 format (16x the size of A4). They were displayed across the venue over three days; each poster gets a day. You get to explain your topic to those who stop by. I had a poster session on Fedora’s RISC-V porting status. It was livelier than I expected it to be (more on it below).
Notes from a few talks
As usual, there were way too many talks; this is just a tiny fraction that caught my attention. (The presentation schedule was a pain to navigate, a long HTML page with no clickable links to sessions.)
CHERI - tackling the “memory safety problem”, Simon Moore et al
This was part of the RVI members-only day, but there’s nothing confidential here. Simon is a professor at the computer architecture research group at the University of Cambridge. His expertise shines through in his talk. The CHERI project, which is ISA-agnostic, has been around for over a decade but it was my first encounter with it. CHERI’s main selling point [PDF] is a promise to better handle memory-related vulnerabilities in C codebases. It relies on hardware protection, and replaces pointers with so-called “CHERI capabilities”. You can read more details here, under “what is CHERI security”.
On the hardware side, from a quick look, they have some developer boards. They also have a port of the kernel and other userspace bits, including a QEMU port. I asked if they plan to upstream it. They want to, but the speaker mentioned a “chicken and egg” problem here, because their extension is not yet ratified. I politely noted that it’s not an issue—they could still submit their QEMU port as an RFC to upstream until their ISA extension gets ratified.
RISC-V “state of the union”, Krste Asanović
Asanović is a professor emeritus at UC Berkeley, he’s also the co-founder of SiFive, and also works at RVI. This was a high-level keynote, with an overview of the past year, progress on standards, and RISC-V adoption.
He also gave an update on RISC-V profiles (a collection of ISA features and extensions that provide most value to most users). RISC-V matrix extensions were the “the liveliest part of this year’s RISC-V standards development”. He, of course, also talked about AI and how RISC-V is becoming the “standard base for new AI accelerators”.
The RISE project: advancing RISC-V Software, Nathan Egge and Ludovic Henry
The main goal of the RISE project is to “accelerate the development of open source software for the RISC-V architecture”. Nathan and Ludovic gave a good overview of the RISE ecosystem, and the accomplishments from the last year. RISE has various working groups for compilers, system libraries, kernel, virtualization, distribution integration, AI & ML, language runtimes and more.
The RISE initiative currently runs a developer appreciation program. Any community developer can formally propose an idea for software porting and, if accepted, you can get some funding for it. Here are some examples of project complexity. (NB: If your employer is a member of RVI, you’re not eligible for this funding.)
Fedora’s porting status, Kashyap Chamarthy
I presented the status of Fedora’s RISC-V port [PDF] as a poster session. Here’s my extended abstract [PDF]. This session was located in a “RISC-V developer zone” for half-a-day. Several people were curious to learn about Fedora’s RISC-V efforts. As a happy accident, an LLVM maintainer stopped by and offered some suggestions to debug some test-suite failures that I ran into on Fedora Rawhide.
The vast majority of Fedora’s packages have already been ported to riscv64. There about 150 packages that still require work before they can be merged into mainline Fedora. Some of these packages have already been built on RISC-V hardware with modified Fedora sources. They need further investigation—e.g. debug failing tests, submit a patch to their corresponding upstream project, work with relevant maintainers, etc. It’s all traditional open-source development. (Refer to the above linked abstract for details.)
Fedora currently builds for RV64GC, a standard 64-bit RISC-V architecture. The switch to the next iteration of the architecture, the RVA23 profile, can happen as soon as compatible hardware becomes available.
Special thanks to Richard W.M. Jones, David Abdurachmanov, Andrea Bolognani, Kevin Fenzi, Jason Montleon, and Wei Fu. And, of course, to the broader Fedora RISC-V community!
If you want to get involved, drop by the Fedora RISC-V Matrix channel. There are many ways to contribute: help port the remaining set of packages to Fedora mainline, test and report bugs in packages you care about, debug test failures, fix bugs and work with upstream, improve documentation, and more.
Python packaging of AI and ML libraries for RISC-V, Trevor Gamblin et al
This effort was about improving the state of ML and scientific-computing Python libraries on RISC-V. They are targeting the developer workflow involving PyPI (via pip) and virtual environments. Their goal is to save developers time (to build and debug) by providing riscv64 binary wheels on PyPI. To that end, they started the wheel_builder project, “a collection of CI build scripts and patches to allow building riscv64 binary wheels for popular Python projects.”
Their current challenges are the long build-times, and some critical upstream projects that don’t test with RISC-V yet, except NumPy. Their next targets are the top-30 PyPI packages, and LLM-related projects such as vLLM, and others. Once PyPI starts to accept riscv64-based binary wheels, and manylinux (a way to distribute binary Python wheels on Linux) supports RISC-V, they want to work closer with upstreams.
This seems like a good example of a successful collaboration with the RISE project, which provided funding and hardware.
Hallway track
As it is for any experienced conference goer, this was the main track for me. Overall, it was educational and productive.
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One of the common terms you hear in the hallways, mostly from the hardware vendors, is tape out — “oh, we’re going to tape-out early next year.” It’s a fancy short-cut to say, “we’ve locked our hardware design, it has passed all verification, and is ready to be sent to the foundry to produce real silicon.”
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Met several engineers from software, hardware, and IP vendors (Canonical, SUSE, Ventana Microsystems, Rivos Inc, SiFive, and more).
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A couple of good chats with Emil Renner Berthing from Canonical; he shared his insights from working with multiple RISC-V boards. I also ran into some old colleagues from the Linux virtualization community, Andrew Jones and Andreas Färber.
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Met a few folks from the RISE initiative: Jefro Osier-Mixon, Nathan Egge, and others.
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Had a good conversation with a couple of conference Program Committee members. They seem to be eager to improve collaboration between academia and industry.
Future
This is my personal riffing, but nothing wild. For RISC-V to become a real threat with teeth, many things need to fall in place: ISA extension developers, hardware and software vendors must all work closely together. The hardware vendors are still figuring out their own destinies. Meanwhile, the software community is trying to do its part by porting all the critical software.
Many of us are looking forward to the next main iteration of hardware based on RVA23, the most recently ratified RISC-V profile. It has critical improvements for virtualization and AI/ML workloads.
To be continued 
Regards,
Kashyap
This report was written by a human, with only minor spell- and grammar-check assistance.